ADPLL Design in VHDL small changes in M, K, N unlocks loop

Status
Not open for further replies.

akurka

Newbie level 1
Joined
Sep 30, 2009
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
SWITZERLAND
Activity points
1,286
ADPLL Design in VHDL

Hi
can You help me ?
I have designed a PLL in VHDL(test bench and UUT in Attachement).
It run With M=16, K=8, N=8 but only small change
of u1 and it go out of lock. What is the reason ?
I try all possible combinations of M,K,N but without success ?
Thank You in advance. Anton
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…