akurka
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ADPLL Design in VHDL
Hi
can You help me ?
I have designed a PLL in VHDL(test bench and UUT in Attachement).
It run With M=16, K=8, N=8 but only small change
of u1 and it go out of lock. What is the reason ?
I try all possible combinations of M,K,N but without success ?
Thank You in advance. Anton
Hi
can You help me ?
I have designed a PLL in VHDL(test bench and UUT in Attachement).
It run With M=16, K=8, N=8 but only small change
of u1 and it go out of lock. What is the reason ?
I try all possible combinations of M,K,N but without success ?
Thank You in advance. Anton