robismyname
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Im using the crystek VCO model number CVCO55BE-2100-2300 for a PLL design.
The tuning voltage is: .3V(min) and 4.7V(max)
The frequency is: 2100MHz(min) and 2300MHz(max)
The tuning sensitivity is: 60 MHz/V
Phase Noise @ 10kHz offset is: -103dBc/Hz
In ADIsimPLL I have to enter the following parameters for the VCO:
Kv=60, V1=.3V, F1=2068MHz , V2 = 4.7, F2 =
To determine F1 I used the following formula:
F1=f(V0)+kV*(V1-V0) = 2068MHz
where f(V0) = 2200MHz
where (kV) = 60 MHz/V
where V1= .3V
where V0 = 2.5Volts
To determine F2 I used the following formula:
F2=f(V0)+kV*(V2-V0) = 2332MHz
where f(V0) = 2200MHz
where (kV) = 60 MHz/V
where V1= 4.7V
where V0 = 2.5Volts
Ok so I place all of the necessary values into ADIsimPLL and I get some erroneous graphs in the time domain. SOmething tells me that this is not right. My question is what is wrong with my lock detect output graph. Why does it look like this? same question for the |freq error| graph(see attachment)
The tuning voltage is: .3V(min) and 4.7V(max)
The frequency is: 2100MHz(min) and 2300MHz(max)
The tuning sensitivity is: 60 MHz/V
Phase Noise @ 10kHz offset is: -103dBc/Hz
In ADIsimPLL I have to enter the following parameters for the VCO:
Kv=60, V1=.3V, F1=2068MHz , V2 = 4.7, F2 =
To determine F1 I used the following formula:
F1=f(V0)+kV*(V1-V0) = 2068MHz
where f(V0) = 2200MHz
where (kV) = 60 MHz/V
where V1= .3V
where V0 = 2.5Volts
To determine F2 I used the following formula:
F2=f(V0)+kV*(V2-V0) = 2332MHz
where f(V0) = 2200MHz
where (kV) = 60 MHz/V
where V1= 4.7V
where V0 = 2.5Volts
Ok so I place all of the necessary values into ADIsimPLL and I get some erroneous graphs in the time domain. SOmething tells me that this is not right. My question is what is wrong with my lock detect output graph. Why does it look like this? same question for the |freq error| graph(see attachment)