ADF4110 PLL Reference Clock

[ali ghafoor]

Can I use a Sinewave Clock Reference of +10dBm with ADF4110 with no damage?? I have operated the PLL with 0 dBm Sine wave Reference Clock, that worked fine. What about +10dBm ??

 

[KlausST]

Hi,

To answer your question i have to look inti datasheets.
Usually there are "absolute maximum rating" where the input voltage is specified.

What does the datasheet say?

Klaus

 

[ali ghafoor]

Datasheet provide maximum rating for CMOS REF clock... For positive cycle it is = 3.3V and for negative cycle it is = -0.3V....With +10 dBm sinewave, positive cycle is OK because peak walue is +1V. But i am confused with negative half cycle. -1V (peak in negative cycle) is out of the limit (-0.3 V)

 

[FvM]

Please notice that the Refclock input will be always AC coupled, means the input signal is centered to Vdd/2.

 

[sophiante]

Why on earth do you want to put so much power into a PLL?
Most PLL's are senstitive on clock inputs. How about one or two resistors?