Hi...
I have been trying to a verilog code for 8 bit signed adder...
To add the negative number we complement it and add it with the positive number with a carry in as '1'.
However when we get the carry out of the above process as zeros then we have to compute the two's complement of the result. For this we have to complement the result and add it with 1. This will consume one more 8 bit adder.
I.E to compute the two's complement of the result if carry out is 0 takes one moe adder. Is'nt there any other better way to avoid this one more adder...
Using a two's complement number format, there is effectively no need for special treatment of any value, you just add binary numbers without considering a sign. Optionally, you can detect overflow from result sign: If both numbers have equal sign and the result has opposite sign, you got an overflow.