Apr 26, 2012 #21 P particleynamics Newbie level 5 Joined Feb 7, 2012 Messages 10 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,347 but y isn't it working here.. am doing my project work on this xilinx and I have to link a fpga to it.. how to get correct output here??
but y isn't it working here.. am doing my project work on this xilinx and I have to link a fpga to it.. how to get correct output here??
Apr 27, 2012 #22 G godfreyl Advanced Member level 5 Joined Apr 18, 2012 Messages 1,974 Helped 632 Reputation 1,266 Reaction score 621 Trophy points 1,393 Activity points 12,772 Instead of this: particleynamics said: module adder(result,operand1,operand2); input signed [31:0]operand1; input [15:0]operand2; output signed [31:0]result; reg signed [31:0] result; always @(operand1,operand2) begin result = operand2 + operand1; end endmodule Click to expand... Try this: Code: module adder(result, operand1, operand2); input signed [31:0] operand1; input [15:0] operand2; output signed [31:0] result; reg signed [31:0] [COLOR="#FF0000"]interim2[/COLOR]; always @(operand1, operand2) begin [COLOR="#FF0000"]interim2 = $signed(operand2);[/COLOR] result = operand1 + [COLOR="#FF0000"]interim2[/COLOR]; end endmodule Last edited: Apr 27, 2012
Instead of this: particleynamics said: module adder(result,operand1,operand2); input signed [31:0]operand1; input [15:0]operand2; output signed [31:0]result; reg signed [31:0] result; always @(operand1,operand2) begin result = operand2 + operand1; end endmodule Click to expand... Try this: Code: module adder(result, operand1, operand2); input signed [31:0] operand1; input [15:0] operand2; output signed [31:0] result; reg signed [31:0] [COLOR="#FF0000"]interim2[/COLOR]; always @(operand1, operand2) begin [COLOR="#FF0000"]interim2 = $signed(operand2);[/COLOR] result = operand1 + [COLOR="#FF0000"]interim2[/COLOR]; end endmodule