library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity examp1_pg165 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sel : in STD_LOGIC;
y : out STD_LOGIC);
end examp1_pg165;
architecture Behavioral of examp1_pg165 is
begin
y<= a + b when sel='1' else
a+c ;
end Behavioral;
+ can not have such operands in this context.
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
y<= a + b when sel='1' else
a+c when sel ='0' else
'z';
For some reason, many VHDL designers want to use std_logic_vectors on ports - there is no need. You can even use signed/unsigned at the top level - its still and array of bits. The reason people do it is many years ago synthesisors only supported std_logic_vector. But this change a long long time ago.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity add_stdlogic_arithlib is
Port ( a : in std_logic;
b : in std_logic;
y : out std_logic;
cy : out std_logic);
end add_stdlogic_arithlib;
architecture Behavioral of add_stdlogic_arithlib is
signal a1,b1,y1:unsigned(1 downto 0) ;
signal y2:std_logic_vector(1 downto 0) ;
begin
a1<= conv_unsigned(a,2);
b1<= conv_unsigned(b,2);
y1<= a1 + b1 ; -- 2 bit unsigned add
y2<= conv_std_logic_vector(y1,2); -- back to std_logic
cy<=y2(1);
y<= y2(0);
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_stdlogic_numlib is
Port ( a : in std_logic;
b : in std_logic;
y : out std_logic;
cy : out std_logic);
end add_stdlogic_numlib;
architecture Behavioral of add_stdlogic_numlib is
signal a11,b11,y1:unsigned(1 downto 0) ;
signal a1,b1:std_logic_vector(1 downto 0) ;
begin
a1 <= '0'& a; -- std_logic vector
a11<= unsigned(a1); -- std_logic vector to unsigned implicit, explicit using to_unsigned not defined
b1<= '0'& b ;
b11<= unsigned(b1);
y1<= a11+b11; -- unsigned sum,2 bit
cy<=y1(1);
y<= y1(0);
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity add_stdlogicv_arithlib is
generic(n:integer:= 4);
Port ( a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
y : out std_logic_vector(n downto 0));
end add_stdlogicv_arithlib;
architecture Behavioral of add_stdlogicv_arithlib is
begin
y<= std_logic_vector(signed'(signed(sxt(a,n+1)) + signed(sxt(b,n+1))));
end Behavioral;
y<= std_logic_vector(signed(sxt(a,n+1)) + signed(sxt(b,n+1)));
Expression in type conversion to std_logic_vector has 2 possible definitions in this scope, for example, SIGNED and std_logic_vector
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_stdlogicv_numlib is
generic(n:integer:= 4);
Port ( a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
y : out std_logic_vector(n downto 0));
end add_stdlogicv_numlib;
architecture Behavioral of add_stdlogicv_numlib is
signal y2:signed(n downto 0) ;
begin
y2<=resize(signed(a),n+1) + resize(signed(b),n+1);
y<= std_logic_vector(y2);
end Behavioral;
std_logic_vector(signed(std_logic_vector'("0")&a) + signed(std_logic_vector'("0")&b));
std_logic_vector("a'left")
The expression can not be qualified by type std_logic_vector
"Try to use" isn't a strict requirement. I'm not working with Xilinx XST, but I would be rather surprized if it doesn't support numeric bit vector types for ports. Even constraint integer types are supported by many synthesis tools. But there may be reasons to restrict the design to std_logic_vector.I read the Xilinx documentation(synthesis guide) and it says that try to use std_logic_vector as port signals.
so, in your knowledge, it does not matter for synthesis these days?
The question often arises with VHDL. The strong typification actually requires a kind of longwinded coding style, lacking elegancy. To give one hint, if you're not satisfied with the set of conversion functions provided by the library, you're free to define a more efficient function on your own.is there more efficient way to do it?
You misunderstood the meaning of the 'left attribute. It's giving bit positions (integer values) rather than bit values. Thus std_logic_vector("a'left") isn't a legal VHDL expression.but, since this is signed, i should be able to use 'left attribute instead of "0". But, I am not able to do so.for example
.You misunderstood the meaning of the 'left attribute. It's giving bit positions (integer values) rather than bit values. Thus std_logic_vector("a'left") isn't a legal VHDL expression.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_stdlogicv_numlib is
generic(n:integer:= 4);
Port ( a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
y : out std_logic_vector(n downto 0);
mthd: in std_logic_vector(1 downto 0));
end add_stdlogicv_numlib;
architecture Behavioral of add_stdlogicv_numlib is
signal y2:signed(n downto 0) ;
signal y3,y4:std_logic_vector(n downto 0) ;
begin
process(a,b,y3,y4,y2,mthd)
begin
if (mthd="00") then
y3<= std_logic'(a(a'left))&a;
y4<= std_logic'(b(b'left))&b;
y<= std_logic_vector(signed(y3)+ signed(y4));
elsif (mthd= "01") then
y<= std_logic_vector(signed(std_logic'(a(a'left))&a) + signed(std_logic'(b(b'left))&b));
else
y2<=resize(signed(a),n+1) + resize(signed(b),n+1);
y<= std_logic_vector(y2);
end if;
end process;
end Behavioral;
Xst:737 - Found 5-bit latch for signal <y2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 5-bit latch for signal <y3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 5-bit latch for signal <y4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
y<= std_logic_vector(signed(std_logic'(a(a'left))&a) + signed(std_logic'(b(b'left))&b));
y<= std_logic_vector(signed(sxt(a,n+1)) + signed(sxt(b,n+1)));
1) this worked when i made three separate programs with each of these options. but, within this mux structure , i get error:
Code:Xst:737 - Found 5-bit latch for signal <y2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Xst:737 - Found 5-bit latch for signal <y3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Xst:737 - Found 5-bit latch for signal <y4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
any ideas why?
also,
works but as i had pointed earlier using std-logic_arith , following gives type qualification error. why?Code:y<= std_logic_vector(signed(std_logic'(a(a'left))&a) + signed(std_logic'(b(b'left))&b));
Code:y<= std_logic_vector(signed(sxt(a,n+1)) + signed(sxt(b,n+1)));
which was introduced simply by declaring an unsigned instead of a std_logic_vector in a random VHDL project.Line 195: Type error near tmp ; current type std_logic_vector; expected type unsigned
Line 207: Type error near poly ; current type unsigned; expected type std_logic_vector
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add_stdlogicv_numlib1 is
generic(n:integer:= 4);
Port ( a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
y : out std_logic_vector(n downto 0);
mthd: in std_logic_vector(1 downto 0));
end add_stdlogicv_numlib1;
architecture Behavioral of add_stdlogicv_numlib1 is
begin
process(a,b,mthd)
variable y2:signed(n downto 0) ;
variable y3,y4:std_logic_vector(n downto 0) ;
begin
if (mthd="00") then
y3:= std_logic'(a(a'left))&a;
y4:= std_logic'(b(b'left))&b;
y<= std_logic_vector(signed(y3)+ signed(y4));
elsif (mthd= "01") then
y<= std_logic_vector(signed(std_logic'(a(a'left))&a) + signed(std_logic'(b(b'left))&b));
else
y2:=resize(signed(a),n+1) + resize(signed(b),n+1);
y<= std_logic_vector(y2);
end if;
end process;
end Behavioral;
entity add_stdlogicv_numlib is
generic(n:integer:= 4);
Port ( a : in std_logic_vector(n-1 downto 0);
b : in std_logic_vector(n-1 downto 0);
y : out std_logic_vector(n downto 0);
mthd: in std_logic_vector(1 downto 0));
end add_stdlogicv_numlib;
architecture Behavioral of add_stdlogicv_numlib is
signal y2:signed(n downto 0) ;
signal y3,y4:std_logic_vector(n downto 0) ;
begin
process(a,b,y3,y4,y2,mthd)
begin
if (mthd="00") then
y2<=(others=>'0'); -- to provide o/p for y2 to avoid latch inference
y3<= std_logic'(a(a'left))&a;
y4<= std_logic'(b(b'left))&b;
y<= std_logic_vector(signed(y3)+ signed(y4));
elsif (mthd= "01") then
y2<=(others=>'0');
y3<=(others=>'0');
y4<=(others=>'0');
y<= std_logic_vector(signed(std_logic'(a(a'left))&a) + signed(std_logic'(b(b'left))&b));
else
y3<=(others=>'0'); -- to provide o/p for y3 to avoid latch inference
y4<=(others=>'0');
y2<=resize(signed(a),n+1) + resize(signed(b),n+1);
y<= std_logic_vector(y2);
end if;
end process;
end Behavioral;
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