You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models
You can actually design a macro model of an ideal DAC to compare the inputs and the outputs. In some environments like Cadence, you can write Verilog A models
thanks for you guys' input. that's actually what i did. i'm just wondering if anyone has made a complete simu testbench/flow, preferrablly for cadence.