[ARM]ADC in triple interleaved mode (STM32F407)

Status
Not open for further replies.

vanika

Newbie level 2
Hello !

My problem is to run Triple Mode, and generally want a detailed understanding of its boundary opportunities, see what you can squeeze out of this module, to build some graphics of his work, etc.

Code dot - [expand]1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

// Triple MODE

ADC->CCR = 0x17; //  Triple MODE

ADC1->CR2 |= ADC_CR2_SWSTART;   // RUN!

Actually, the result is the simultaneous operation of all three ADC, but in the data register Multi Mode CDR can be observed only zeros...

This result is obtained when the input sine wave has a frequency of about 7 kHz. It seems to me that I overlooked in the field sample rate.
Correct if I'm wrong

Last edited by a moderator:

Status
Not open for further replies.