AD8651 unity gain operation

[elsalty]

I am using an AD8651 in a non-inverting unity gain configuration. I am running off of +5V and GND. The data sheet here:

https://www.analog.com/static/imported-files/data_sheets/AD8651_8652.pdf

indicates the GBW is 50MHz, the input bias current is 10pa and on page 9 shows the closed loop gain for G=1 out to beyond 50Mhz. The load is the non inverting input of a second AD8651 (i.e. very high impedance). I wanted to use it with several gain options so the feedback resistor (Rf) is 10k and the resistor to Vmid (2.5V) is either 1)open for unity gain, 2) 10k for gain of 2, or 3) 4.99k for gain of 3. I have just been testing with the unity gain and inputting a 0.5 Vpp sine wave centered about Vmid (2.5V). When I increase the frequency to beyond about 50khz the output magnitude starts to increase significantly. By the time I am at 1MHz the output signal is 1.5x the input signal. I have found that if I replace the 10k feedback resistor with a 0.0 ohm resistor this problem goes away.

I was just wondering if anyone could help me figure out why this is happening? If I had to guess I would assume it is something with the input capacitance (6pF) but I am not sure. Thanks for any suggestions.

 

[Dan Mills]

The usual reason for that behaviour is capacitence to ground or VMid from the inverting input, cure is to place a small capacitor across the feedback resistor (10pF or so).

10K is however a VERY large feedback resistor for an amplifier having 50MHz unity gain bandwidth, 1K or less would be more my instinctive choice.

In general you need to be very careful of capacitive loading of the inverting input pin, it far more then the non inverting once can cause stability headaches.

Regards, Dan.

 

[D.A.(Tony)Stewart]

You must evaluate the RC time constant on the (-) input for stray capacitance in parallel with input capacitance. The will boost the HF response. Guarding methods are often used to reduce stray capacitance, but at 50MHz CMOS with high impedances outputs limiting the smallest Rf possible causes frequency response issues.

Can you post the layout?

 

[elsalty]

That is a great point. If the Rf is 10k and the input capacitance is 12pf (amplifier + stray) then the time constant for that is 120ns (fc = 1.3MHz).

I can post the layout tomorrow.

 

[crutschow]

If the amp input capacitance is 6pF then the added circuit board wiring strays would bring that up to 15pF or more. The -3dB point for 15pF and 10kΩ is 1MHz so it's not surprising that you see peaking starting to occur below that frequency. The feedback resistor and the stray capacitance act like a low-pass filter to the feedback voltage. This means the output voltage has to increase to maintain the feedback voltage at the inverting input equal to the signal voltage at the non-inverting input (which is what the op amp always tries to do). The 3dB of feedback voltage rolloff at 1MHz will give 3dB of peaking at the output which is near the 3.5dB (1.5x) factor you observed.