Active HDL 10 released

Similar threads

• E

  Evaluation board with 10 Gbps Ethernet

  • Started by engr_joni_ee
  • Aug 9, 2023
  • Replies: 12

  PLD, SPLD, GAL, CPLD, FPGA Design
• L

  [SOLVED] arria 10 ds-5 not recognize the target

  • Started by levnu
  • Aug 31, 2023
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• T

  Need help regarding HDL terminology

  • Started by Tajira
  • Nov 28, 2022
  • Replies: 1

  PLD, SPLD, GAL, CPLD, FPGA Design
• programming MFRC522 with hdl

  • Started by wowpro7
  • Aug 8, 2022
  • Replies: 5

  PLD, SPLD, GAL, CPLD, FPGA Design
• B

  verilog .V file errors "Verilog HDL Implicit Net warning"

  • Started by bteddy1
  • Jul 27, 2022
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design