Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Actel design flow and timing constraints

Status
Not open for further replies.

buenos

Advanced Member level 3
Joined
Oct 24, 2005
Messages
960
Helped
40
Reputation
82
Reaction score
24
Trophy points
1,298
Location
Florida, USA
Activity points
9,116
constraint file synplify actel

hi

Actel recommends to set up timing constraints in the "Designer" which is the P&R tool. But, if I change the VHDL code, resynthesize, and open the designer for P&R again then the previously set-up constraints disappear. This is because the synthesis tool overwrites them to the default values.

If I add a conctraint SDC file in synplify synthesiser project, then its OK, but if I change the VHDL code and open the Synplify again, the SDC file has to be added to the project again because the Libero regenerates the Synplify project - without the SDC file.

If I add a new SDC file in the Libero, then it will appear in the Synplify, but will not contain the clocks and other nets automatically, it will be only an empty file. If I open it in the Synplify/Scope it will be an empty spreadsheet. I dont want to type everything manually.

So, how to manage timing constraints in the Actel-Libero/Synplify/Designer flow?
 

synplify timing constraint

Hi,

Before invoking synplify for synthesisyou can add constraint file (*.sdc) in which you can write timing related constraint like false path, clock generator, input delay, output delay...etc.

then if you invoke designer Libero generated SDC file will copies that constraint form synplifile constraint file and then while doing place and rout you need not to give again SDC file beacuse tool took automatically generated constraint file, which have all constraint you have given in SDC file while synthesizing.

Hth,
--
Shitansh Vaghela
 

actel specifying clock constraints

hi

thanks,

so, basically i can not create my constraints in the scope-spreadsheet and keep it, i only can write the constraint by hand. its not too convinient.
or maybe i could create it in synplify-scope, then add it to the libero project later...
 

actel designer input delay constraint

Hi,

at this stage even i dont know whether it is possible or not but if i come to know sure will tell you, and if you come to kmow before me please share it.

Thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top