buenos
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constraint file synplify actel
hi
Actel recommends to set up timing constraints in the "Designer" which is the P&R tool. But, if I change the VHDL code, resynthesize, and open the designer for P&R again then the previously set-up constraints disappear. This is because the synthesis tool overwrites them to the default values.
If I add a conctraint SDC file in synplify synthesiser project, then its OK, but if I change the VHDL code and open the Synplify again, the SDC file has to be added to the project again because the Libero regenerates the Synplify project - without the SDC file.
If I add a new SDC file in the Libero, then it will appear in the Synplify, but will not contain the clocks and other nets automatically, it will be only an empty file. If I open it in the Synplify/Scope it will be an empty spreadsheet. I dont want to type everything manually.
So, how to manage timing constraints in the Actel-Libero/Synplify/Designer flow?
hi
Actel recommends to set up timing constraints in the "Designer" which is the P&R tool. But, if I change the VHDL code, resynthesize, and open the designer for P&R again then the previously set-up constraints disappear. This is because the synthesis tool overwrites them to the default values.
If I add a conctraint SDC file in synplify synthesiser project, then its OK, but if I change the VHDL code and open the Synplify again, the SDC file has to be added to the project again because the Libero regenerates the Synplify project - without the SDC file.
If I add a new SDC file in the Libero, then it will appear in the Synplify, but will not contain the clocks and other nets automatically, it will be only an empty file. If I open it in the Synplify/Scope it will be an empty spreadsheet. I dont want to type everything manually.
So, how to manage timing constraints in the Actel-Libero/Synplify/Designer flow?