... if the PMOS is in accumulation, doesn't that mean that the charge carriers in the bulk are majority electrons? So shouldn't they have high mobility, just like minority electrons in an inverted NMOS channel?
How so? The PMOS is in an Nwell, and the gate is positive, electrons accumulating in an Nwell is accumulation, not inversion.But re. the PMOS action the channel is inverted
Yes, if you call the accumulated electrons in the Nwell a channel (I wonder if it's okay to use the term for accumulated charges instead of enhanced/inverted charges), then the P+ S/D regions form diodes which would have no bias, so that would block charge transfer (or at least decrease capacitance) to those regions. However, I will also be tying the Nwell to gnd along with the substrate and S/D regions, so the Nwell contacts are another path for the electrons. Will those P+ regions still get in the way then? I guess they would then have to pass through charge-neutral Nwell, which would have a high resistance....i.e. there exists a junction between channel and the S/D regions, which prevents a quick supply of electrons, means you may have a good DC cap, but not a good ac cap.
Thanks, but neither of these seem to address the issue of high frequency response for an accumulation PMOS capacitor? The first pdf only refers to PMOS cap in inversion, the second pdf doesn't refer to frequency response or ESR.
Right, I wrote so: accumulation re. the Nwell. If you regard the PMOS action, however, this is an inversion of its normal behaviour: not a p-channel is built up, but an n+ "channel" - an n+ accumulation region instead of a p+ channel. Perhaps a misunderstanding.The PMOS is in an Nwell, and the gate is positive, electrons accumulating in an Nwell is accumulation, not inversion.
Yes, if you call the accumulated electrons in the Nwell a channel (I wonder if it's okay to use the term for accumulated charges instead of enhanced/inverted charges), then the P+ S/D regions form diodes which would have no bias, so that would block charge transfer (or at least decrease capacitance) to those regions. However, I will also be tying the Nwell to gnd along with the substrate and S/D regions, so the Nwell contacts are another path for the electrons. Will those P+ regions still get in the way then? I guess they would then have to pass through charge-neutral Nwell, which would have a high resistance....
If I remove the P+ regions, then I guess I'm left with a simple AMOS cap. Nothing wrong with that physically, but I don't think Cadence will be able to extract it properly, and LVS would probably throw a fit. Not sure about the foundry...
Thanks, but neither of these seem to address the issue of high frequency response for an accumulation PMOS capacitor? The first pdf only refers to PMOS cap in inversion, the second pdf doesn't refer to frequency response or ESR.
Okay, different "inversion," understood.Right, I wrote so: accumulation re. the Nwell. If you regard the PMOS action, however, this is an inversion of its normal behaviour: not a p-channel is built up, but an n+ "channel" - an n+ accumulation region instead of a p+ channel. Perhaps a misunderstanding.
Yeah the nwell AMOS cap is likely my best bet, if I can get it to work in my process. It's not mandatory that it extract/LVS properly, so long as it actually works. I've been told that it can be implemented, but none of the tools will tell you if you're implementing the layout correctly, and I have no example layouts to go on.For a good ac cap you should use an NMOS in Nwell, s. item 5.3: N+ over Nwell gate capacitor in the (p. 5). Such an accumulation cap can quickly supply majority carriers and doesn't depend on the slower electron supply via the S/D junctions or the relatively high-ohmic Nwell bulk.
Extraction and LVS may be a problem. Our process PDK supported such an N+ in Nwell MOSCAP.
Right, it's sort of an odd issue to explore. But also odd that my process doesn't accommodate the nwell amos properly since it's obviously useful and can be implemented.Yes, I know, not too directly, sorry for that. But the first one tries an estimation of the frequency response of a PMOScap (p. 75 resp. 5 of the PDF), and the second one at least shows the N+ in Nwell RF MOSCAP solution.
... none of the tools will tell you if you're implementing the layout correctly, and I have no example layouts to go on.
My process is ami05 and I'm using the NCSU CDK. Putting poly over Nactive in an Nwell throws a DRC error saying "poly cannot overlap ohmic diffusion." So it thinks I'm making a resistor. I'm not sure if this is a design rule I can ignore. Best I can do without a violation is something like this:Try the layout shown at item 5.3: N+ over Nwell gate capacitor of the above PDF: A square "ring" of N+ S/D diffusion, poly gate slightly overlapping it (as to the rules).
I'm pretty certain that poly contacts can't go above active. Certainly not with MOS transistors, so probably not for MOS capacitors either.In your 0.5µm process you could perhaps even use poly contacts over the gate area, which would further reduce ESR.
If you think it's important, you could try and get a waiver from the AMI fab.I'm not sure if this is a design rule I can ignore.
Right. Only once I've been allowed by waiver to contact poly over active - and for polycaps only.I'm pretty certain that poly contacts can't go above active. Certainly not with MOS transistors, so probably not for MOS capacitors either.
Right, the electrons at the oxide interface will be fast, but what's not clear is the path they have back to the negative biased terminal of the capacitor. It can't conduct directly back to the P+ active regions, due to the PN junction there, so it must pass through the Nwell back to the Nwell contacts, which will increase ESR.If it's a PMOS in Nwell, you should operate it in accumulation: in contrast to my ): View attachment 116828
If high frequency is your concern, you might look at layout
styles which minimize the channel resistance (assume this
dominates the sum of Rg+Rds(on)/2 which is your ESR).
I make decoupling MOS caps fingered, over-square (W >>L)
to drive doen the access resistance, I never make a bulk
decoupling cap as a square slab. I also put criss-crossing
Met1 over poly and Met2 over Met1 for some better-HF
upside (even though low-value, it's something).
I'll usually pick something like a plurality of 20/4 fingers
but I never really bother to look at fine optimization. You
could, though, play with L and nf trades with an eye to
areal capacitance (net) and corner frequency.
If you operate in inversion, you have also the channel-
body capacitance in parallel which could add some bulk
C (probably not great quality, but it's there). Assuming body
is one supply and bulk, another. If you used PMOS in NWell
you have actually two junction caps and a MOS cap and
any overlaid metal capacitance (but this may not be as
good for HF decoupling as the NMOS with its lower channel
resistance, despite more C - you'd need to roughly double
C keeping R the same, to have the same corner f, right?
I don't think the junction caps will be as nearly as dense
as the MOS).
But anyway, stack what you've got as tall as you can stand.
MIM over MOS, even, if your technology allows topography
under MIM (and if you have a MIM, which C5 base flow may
not offer).
Right, the electrons at the oxide interface will be fast, but what's not clear is the path they have back to the negative biased terminal of the capacitor. It can't conduct directly back to the P+ active regions, due to the PN junction there, so it must pass through the Nwell back to the Nwell contacts, which will increase ESR.
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