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AC plot of OTA(gain vrs frequency plot)

Adel Rein

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I did an ac analysis plot on a two stage OTA with the plot shown below
Screenshot from 2021-09-25 19-24-49.png

Is the graph correct, because I need to determine the gain bandwidth product and I am finding it difficult to find the gain bandwidth product. I am expecting a gain bandwidth product of 25M
Below is the schematic
Screenshot from 2021-09-25 19-34-43.png
 

frankrose

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let me some thoughts:
1, your bias current is higher than the mirrored current for the OTA diff.pair tail. Not so smart, since big percent of available supply current is not used for bandwidth (higher diff.pair current = higher bandwidth)
2, W/L of diff.pair is smaller than PMOS load W/L, not so good, since gm of diff.pair determines bandwidth, it should be high, PMOS load W/L determines DC gain, and its gm should be low.
3, apply negative feedback to set output DC operating point in AC analysis. Generating a differential input voltage in open loop is not the best way, since only strange sizing of devices can lead to an operating point where luckily all devices are in active/saturation region.
To simulate openloop gain connect a huge ideal inductor rather between OTA output and inverting OTA input (1H-1kH), and a huge ideal capacitor between inverting input and GND (1F-1kF). Apply an AC source (1V magnitude) with a DC common-mode voltage (VDD/2=0.9V) on non-inverting input and it will set correct DC operating point in AC analysis. Below an example:
4, reduce PMOS widths, they are too big, they produce big C parasitics which can decrease bandwidth
5, if bandwidth is still low, increase current
6, I recommend you to set L for every device a 1um, than play with W.
 

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