srish
Newbie level 6
Why we need Abstract class in our Testbench.........what is advantage of using it.......normally in its child class we declare the functions or tasks with full functionality then why to create a abstract class???
Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
The abstract class represent a contract that must be fulfilled (implemented) before it can be used. This way, you can have code with class variables of the abstract type assigned with handles to extended class objects, and that code does not need to know anything about the extended classes. "Abstract" means the class has no use as an object by itself, and SystemVerilog makes it a compiler error if you try to construct an abstract object.
Read my DVCon paper attached to **broken link removed** for an application of abstract classes.
task does_something();
bfm_h.setBitPeriod(5);
bfm_h.setNBits(8);
repeat(10)
bfm_h.send($random);
endtask