About voltage doops of the S/H @ hold phase

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analogman

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Hello.

I am designing the S/H circuit.
But, I have a trouble now.

In hold phase, the holded voltage is drooping!
Is it natural ? I think it causes less acurate...
I use 250fF for sampling cap.

There is no teacher to advise me.
Any advise or solution, please.
Thank you ...
 

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