about two clks and sampling timing

[meisuo_1985312]

about two clks' problem

hello!
if thers is a design that i need to use a basic clk to sample another signal,and the sampled external signal is always changing,usually which is not a question.but when the basic clk and the external signal are changing at the same time (for example,the basic clk simples when ringsing edge,when the external signal are changing )then the signal after being sampled is unknown!i know this is about setup time and hold time ,but i can't i can't control the external signal,then what should i do?
and if the signal is a FSM's input,then my FSM's state become unkown too!
i'm sorry for my poor English.
my program is big ,thers is a simple example to descripe the same problem as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test_for_holdtime is
Port ( clk : in STD_LOGIC;
pclk : in STD_LOGIC;
state_signal ut STD_LOGIC_vector(1 downto 0);
pclk_out : out STD_LOGIC);
end test_for_holdtime;

architecture Behavioral of test_for_holdtime is
type STATE_TYPE is (s1, s2, s3,s4);
signal presState, nextState: STATE_TYPE;
signal buff_pclk_out :STD_LOGIC;
begin
pclk_out<=buff_pclk_out;
process(clk,pclk)
begin
if clk'event and clk = '1' then
buff_pclk_out<=pclk;
end if;
end process;

process(clk,nextState)
begin
if clk'event and clk = '1' then
presState<=nextState;
end if;
end process;
combone_processrocess(presState,buff_pclk_out)
begin
case presState is
when s1 => state_signal<="00";
if buff_pclk_out = '1' then
nextState <= s2;
else
nextState <= s1;
end if;
when s2 => state_signal<="01";
nextState <= s3;
when s3 => state_signal<="10";
nextState <= s4;
when s4 => state_signal<="11";
nextState <= s1;
when others =>nextState <= s1;
end case;
end process;
end Behavioral;