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About the Testbench and Testcase?

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Newbie level 4
Apr 18, 2011
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Who can tell me the different points between the Testbench and Testcase in details?
I'm fell confusion about that!:???:


Test Plan : It is your plan to test the DUT(Design Under Test). That is, all the necessary tests to be done on the DUT to check all the features.

Test Bench : It is module to give the stimulus (input) to the DUT. In this you will drive the values as per your requirement. you can have tasks and assign values by passing values through arguments.

Test Case : Now you have different tasks in the test bench and the test environment. So from test case you can pass the values through the arguments. For different fetures you will have different values to be driven. so by looking the test plan, you can write a test case and drive the values to the tasks in test bench or test environment and drive the srimulus to the DUT to check that feature.

---------- Post added at 13:10 ---------- Previous post was at 13:09 ----------

The Circuit that you are willing to verify is know as Design Under Test (DUT).

In order to test this design you need to prepare a plan of action as how to birfucate and check for various features supported by the design --> this is will be your test plan.

In order to check the features of DUT you need a means for generating the input and checking the output of DUT, Which needs binding of the DUT, Coverage etc and also granularity of interface to the Verificaiton Engineer.--> these aspects are covered in the Testbench

The DUT is capable of supporting more than one feature, in which case you cannot come up with seperate Testbench to verify each feature so you provide a means of configurabilty to control the testbench behaviour which is done through the test case --> A configuration which is used to verify a certain functionality of the DUT.
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Thank you for your help,so far,I have known the conception of the Testbench & Testcase.Maybe,I need more practice in the verification!
Best regards!

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