I don't think so: 2,5V/65nm create an electric field strength of 38 V/µm , far above the critical electric field resulting in velocity saturation.
This increases the probability of impact ionization effects ("weak avalanching"), creates additional drain-bulk current contribution, hot carriers which create damage at the Si-SiO
2 interface (increasing the interface-state density) or which even may become trapped in the oxide, so changing the oxide charge, and -- over a sufficiently long period of time -- these effects can permanently increase the threshold voltage and lower device
gm (hot-electron device degradation), s. e.g.
David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design" pp. 146-148 .
LDD (lightly doped drain) process option can reduce this risk (also s. the a.m. section in the Binkley book).
Max. V
gs depends on
tox, the gate oxide thickness. Without an
HV tox process option, Vgs will also be limited to the recommended supply voltage of 1.2V .