About the supply voltage of an inverter in tsmc 65nm LP process

[easyads]

Hi
An inverter with minimum channel length(L=65nm) in tsmc 65nm LP process is designed. The recommended supply voltage of the inverter from tsmc is 1.2V.
(1) If the inverter is used as a static inverter, could the supply voltage vdd be more than 2.5V?
（2） IF the inverter is used as an clk buffer （Fclk=80MHz0), could the supply voltage vdd be more than 2.5V?

I have reversed an third party chip. In the chip, there is some inverters designed with minimum length(L=65nm), but the supply voltage of these inverter should be more than 2.5V by circuit analysis. Can this be reasonable?

Thanks .

 

[varunkant2k]

See , you have to understand that what is the actual purpose of the inverter.
1. To drive some load, or to provide logical signal at no/very low load.
2. Its a buffer when you drive a big device from inverter and then it should have some voltage and current strength.
This comes with big inverter sizes and high supply voltage.
3. Digital voltages ( where no load) its good to have minimum transistor length, but in case of analog ( here my mean is you have certain loading) you should have 3-4 times of transistor min length.

 

[erikl]

Can this be reasonable?

I don't think so: 2,5V/65nm create an electric field strength of 38 V/µm , far above the critical electric field resulting in velocity saturation.

This increases the probability of impact ionization effects ("weak avalanching"), creates additional drain-bulk current contribution, hot carriers which create damage at the Si-SiO₂ interface (increasing the interface-state density) or which even may become trapped in the oxide, so changing the oxide charge, and -- over a sufficiently long period of time -- these effects can permanently increase the threshold voltage and lower device gm (hot-electron device degradation), s. e.g. David M. Binkley "Tradeoffs and Optimization in Analog CMOS Design" pp. 146-148 .

LDD (lightly doped drain) process option can reduce this risk (also s. the a.m. section in the Binkley book).

Max. Vgs depends on tox, the gate oxide thickness. Without an HV tox process option, Vgs will also be limited to the recommended supply voltage of 1.2V .

 

[salar2000]

hi
I need very necessary to have 65nm cmos (IBMs) technology for simulation on hspice
please help me

 

[erikl]

https://www.edaboard.com/threads/112170/

 

[karthiktj]

Hi easyads,
As long as you ensure that the voltage across any two terminals of the device is withing 1.2V, you are safe. For a conventional inverter, if you use 2.5V, its going to cause reliability problems; the devices of the inverter will break down.