about the simple Clocked RS NAND Latch

[zydgyy]

This is a description about the clocked RS NAND Latch:

A major problem remaining is that this latch circuit could easily experience a change in S and R input levels while the CLK input is still at a logic 1 level. This allows the circuit to change state many times before the CLK input returns to logic 0.

, it is an excerpt from http://www.play-hookey.com/digital/clocked_rs_latch.html!
I just understand fully about, why cant this circuit change state manay times! Isn't it allowed to change state as long as the CLK is activate?!!!!?

 

[ark5230]

What it says it what it mean and is correct too.

 

[DigitalLogician]

here is a much better place to learn about the Clocked RS NAND Latch **broken link removed**. **broken link removed** is a lot easier to follow than play-hookey. I use teahlab extensively. It's the best digital site I have found yet. You should check it out.