how to improve the ripple rejection of a voltage regulator?
this is a important for a voltage regulator.
use a cap. at the feedback network or reduce the erramp's current?
moderator,your suggestion is to use a pre-regulator,aren't you?
I just use a zener diode as my reference,the comman npn-pair opamp for the erramp.It's ripple rejection is only 47dB.
I was suggesting using two low drop out IC regulators. Another trick is to reduce the ripple into the regulators with larger capacitors before the regulators. I have on several occasions modified commercial supplies by adding more capacitors.
Another trick with home made regulators with op amps is to power up with the reference powered from the input and then power it from the output. This is done with resistor-diode networks.
You can try bigger output capacitor with smaller ESR resistor to improve ripple.
When you parallel two capacitors, the capacitance will increase and ESR will decrease as well.
1. High bandwith
2. High gain
2. Good PSSR of the error amplifier
Generally speaking LDOs suffer from poor rejection due to the pass element wich is usually a PMOS, if you can cope with higher voltage drop, consider using an NMOS as a pass element.
To get a low drop voltage regulator using an NMOS transistor as pass element you must use a dc/dc converter (such as charge pump) in ordet to generate a gate voltage higher than the drain voltage; in this way you may achieve a very low drop vreg but generally speaking the lower is the drop, the poorer is the svr. An NMOS is naturally less affect by the supply noise (it appears as drain-gate voltage rather than source-gate voltage as in PMOS regulators) but driving it through a dc/dc converter generated voltage generate a great deal of problems.
What is the capacitor value you have added on chip at the regulator output?
Nomally, 200~500pF is necessary.
I don't think the AMP u used should have a large BW.