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about the magnitude of parasitic capacitance between IO pads and FPGA pads?

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zhangljz

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Hi,

I'd like to simulate the IO buffer. The chip needs input and output from FPGA. Chip package will be PGA. Could anyone tell me the capacitor between IO pads and FGPA in general? several pF or tens of pF, or something others?

Thank you!
 

What are you trying to simulate with ?
 

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