About the logic level change in DDR SDRAM

[EDA_hg81]

According to the DDR SDRAM datasheet from Micron, the logic level of CKE is going to be changed from LVCMOS low to SSTL 2 high during system initialization.

How I can do this in FPGA programming.

Thanks

 

[Iouri]

you need to assign you IO standard in your USF file (I assume you are using Xilinx)

 

[EDA_hg81]

I know I have too assign it in UCF file.

but How I can change the logic level during the operation from LVCOMS to SSTL_2?

 

[Iouri]

there are only two logic levels high and low, all you need to do it just switch from low to high, because you are doing this during init stage it doesn't really matter which standard is that, as far as you within limits of 2.5V being logical high

 

[EDA_hg81]

Thank you.

I fell more confidence.