Hi:
I have the PowerPC 460 Core(whic don't support mulit core instruction),but now I want to finish a design which have dual core, so if I connect the L2 cache to two 460 core and on the other side of L2 cache connect to the system bus,is this scheme feasible?
I suddenly realized that if connect the L2 to the two 460 core directly,there is a problem about the L1 cache coherency,if I modify the L1 cache,is there some other problem?