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about testbench automatically writer

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May 16, 2001
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Now, in simuliation of HDL (vhdl and verilog),testbench is very important, i have used the sync@d's te*stbencher pro* to generate testbench automatically in windows OS, but it don't work fine in solaris OS, it work too slowly with bad perform.
Can anyone introduce a new tools to generate testbench automatically,both in windows or UNIX OS are wellcome. thanks.

I think that tool could be good at Win Environment.

Could you upload sync@d's te*stbencher pro* ?

I can try to find out the problem is ~~

Hi, nmtr
I think the best way is to write testbench by our hand .and the generator is just to generate the framework of the testbench, not include the detail stimuli.

agree with linuxluo. What do you (1st poster in this topic) mean by "automatically". Well your automatic testbench generator would at least instantiate its template for creating testbenches. Additionally it could have one or more of the following features:
(a) read a timing diagram to create the stimuli and the result testing in way like ATE (Automatic Test Equipment)
(b) create bus functional model from timing diagram (could be better)
(c) easy creation/modification of vector (golden) files
(d) programming like features to create reference model (to make BFM)

All these can also be done be hand. Personally by manually creating the testbench (self-checking, or using BFM as procedure or whatever) is a more reusable technique, than changing some weird descriptions of a PROPRIETARY form.


can you tell me what is ATPG(automatic test pattern generator) and is there such tools

Very-very expensive tools that produce massive numbers of test vectors to verify your netlist at the final stages of chip production. Since in ATPG there doesn't exist a strong standard yet, each vendor provides proprietary facilities.

Costs are $50,000 for some of them.

I would surprised if such (production-level) were made available in this forum.


The prevailing ATPG tools for ASIC today are Synopsys 'TetraMax', and Mentor 'DFT Advisor / FastScan'

10x a lot
can you tell me something about fault simulation tools

NO, ATPG is not exactly that you wanted.
It's the test pattern(vector) generation tool. It used to test the IC released from foundry through IC test equipment. If the test passed, it means the returned IC is functionlly equivalent as your netlist. Alough it has some DFT insertion function, but it can not do testbench work to test the function of your netlist is correct or not.

I have heard the vera is good testbench automation tool, you can try it. But you still need do much hand-write codding works.

Hi, CatKing
I have used vera from syn*psys. I think vera is a powerful and useful tools for mdelding BFM, but it's difficult for a newbie. I spend 7 days to learn it and can't master some feature.
And the atuo generator feature of vera is the same as ACtivehdl on the windows platform. I don't think it's a very useful feature.

Thanks all.
i have cocerned on the the testbench genertor, because verification is a key work in ic design espicallly in soc era. i have read some documentments about it. Some special HVL language like vera is commended by somebody and companies, and OVL is commented too.
with some formality verify mechanism tools. Any of them are verification oriented and without vectors.
i think those tools and work is belong to a special testing engineer, other than RTL code engineer. if a RTL code engineer have to write those by himself, the work is terrible.
i don't know in IC company( i am student) how much test work of writing testbecnch is done by RTL code engineer. In my opinions, code engineer will use the testbechs built by testing enginerr for big component vectored or vectrolessed. for small components he can write some vertored testbench by himself, by hand or some tools like testbenchPRO for sync@d.
any comments are welcome.

is there anyone whi is worked with
Verilog Fault Simulation - HyperFault Fault Grading
or Verifault-XL from Cad*nce

nmtr said:
Thanks all.
i have read some documentments about it. Some special HVL language like vera is commended by somebody and companies, and OVL is commented too.
with some formality verify mechanism tools. Any of them are verification oriented and without vectors.


Hi nmtr,

Can you please upload the document about verification, it seems very interesting.

Thanks in advance. :roll:

It's not foolproof, but this tcl/tk testbench generator I wrote does the testbench shell pretty nicely. As I mention in the help function, if you don't like it, hey, you have the source.

Here u can use perl language to generate the above automatic test bench generator, well it just creates the outline of the test bench but not the stimulus and other main stuff, max can help upto a clock generator, that too upto a predefined point.


i hav some doubt regarding the testbench...

if we can do waveform simulation.... y we need to do testbench???


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