jiang
Advanced Member level 4
Hi guys,
I useed synopsys synthesis tool to synthesize the verilog files.
I redefined the parameter of sub-module in top module,
but design analyzer could not find the sub-module in top module.
Design analyzer modified the instance in top module by adding '_param_x.'
How do I fix this problem?
Jiang
I useed synopsys synthesis tool to synthesize the verilog files.
I redefined the parameter of sub-module in top module,
but design analyzer could not find the sub-module in top module.
Design analyzer modified the instance in top module by adding '_param_x.'
How do I fix this problem?
Jiang