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about synospys synthesis problem

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jiang

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Hi guys,

I useed synopsys synthesis tool to synthesize the verilog files.
I redefined the parameter of sub-module in top module,
but design analyzer could not find the sub-module in top module.
Design analyzer modified the instance in top module by adding '_param_x.'
How do I fix this problem?

Jiang
 

jiang

Advanced Member level 4
Joined
Dec 31, 1999
Messages
111
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0
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0
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0
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1,296
Location
Taiwan
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855
jiang said:
Hi guys,

I useed synopsys synthesis tool to synthesize the verilog files.
I redefined the parameter of sub-module in top module,
but design analyzer could not find the sub-module in top module.
Design analyzer modified the instance in top module by adding '_param_x.'
How do I fix this problem?

Jiang
nobody answers me.
finally, I changed all parameters needed.
I still hope that someone can give an efficient way to fix this problem.
Maybe this information can help many people.
 

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