about synospys synthesis problem

[jiang]

Hi guys,

I useed synopsys synthesis tool to synthesize the verilog files.
I redefined the parameter of sub-module in top module,
but design analyzer could not find the sub-module in top module.
Design analyzer modified the instance in top module by adding '_param_x.'
How do I fix this problem?

Jiang

 

[jiang]

Hi guys,

I useed synopsys synthesis tool to synthesize the verilog files.
I redefined the parameter of sub-module in top module,
but design analyzer could not find the sub-module in top module.
Design analyzer modified the instance in top module by adding '_param_x.'
How do I fix this problem?

Jiang

nobody answers me.
finally, I changed all parameters needed.
I still hope that someone can give an efficient way to fix this problem.
Maybe this information can help many people.