about spur of PLL! strange !

[lifusu]

hi!
i design a pll:
f_out=240Mhz;f_ref=12Mhz
it ought to have spurs at 240+-12MHz, 240+-24MHz etc.
but there are spurs at 240+-6MHz, 240+-18MHz too, i dont know why!

**broken link removed**

 

[D.A.(Tony)Stewart]

u must show schematic.. but if mixer is digital, then sub harmonics are possible with intermod. products.

But are you using divide /20 in PLL is the mixer /10 then /2 with symmetrical signal?
IS it possible digital noise from counters is getting into VCO?

 

[lifusu]

yeah ,i use divide /20 in PLL is the mixer /10 then /2 , and now verilogA module to replace the divider, the spur is normal .
and how to solve this problem?
thx!

 

[D.A.(Tony)Stewart]

cannot comment on design if unknown
.. check both inputs to mixer and define mixer design,

 

[dick_freebird]

Consider the nature of the square wave signals.

You seem to be looking to the fundamentals, which is
for linear small signal type systems.

But every digital edge presents a current impulse to
the system, times two per cycle, so a 3M clock can
make 6MHz tones.

Conversely your reference clock might very well be
used, divided down, to run internal logic stuff and the
"heartbeat" will get all over everything.

Phase-lagged clock perturbations can contribute to
subharmonic behaviors through bondwire coupling,
a ground-bounce that happens at just the wrong time
to advance / retard / advance the edge transition
from the outside world, etc. Placement of the RF
inputs, segregating them inside ground cages etc.
is desirable. Same concerns apply to the test setup.