Switch phasing must ensure there is no overlap which
would ohmically mess up the transfers-of-charge.
4nF is pretty chubby. Maybe FET on resistance makes
a time constant that is lower than your sampling pulse
pulse width and so incapable of a clean single pulse
sample. Zoom in on a single clock cycle and assess
the sampling settling, and the hold droop.
But how you expect to control -15V signal with FETs
operating between Gnd and positive supply, I do not
see offhand. Maybe you should back up a few steps
and figure out the regions where those FETs have
actual, proper authority / operation - including that the
controlling sources are doing the right thing at those
various bias-points.