About PLL loop bandwidth.

[Analog_starter]

loop bandwidth pll 1/10 stability why

Hi all,

I have a question about the PLL loop bandwidth:
Is the bandwidth narrower then the jitter more little? If it is ture, why
not always choose the very very narrow loop bandwidth but the 1/10~1/20
input frequency?

Thanks & Best Regards
Analog_starter

 

[flatulent]

The PLL is a classical feedback control system. Inside the bandwidth the output jitter tracks that of the reference. Outside the bandwidth the jitter is that of the VCO.

So the bandwidth you select depends on the situation.

There are three further influences on the selection. One is reference sidebands on the output. Another is loop stability. The third is lockup time. In FM demodulators the audio frequency range is a factor.

 

[Analog_starter]

Thank u.
So do you mean if the input reference is rather clean I can choose
the bandwidth larger that is advantageous to suppress the VCO jitter?

And for the three further influences, could you give me more details?

Thanks & Best Regards
Analog_starter

 

[eng_Semi]

As the loop BW increase, the attenuation of the reference sidebands decrease.

As the loop BW increase, the loop settling time decrease.

 

[khouly]

yeah if u use a very clean reffernce so u can increase the bandwidth of the loop

as u increease the BW of the loop , the loop transfer function of the phase noise coming form the oscillator is high pass filter response so as u increase the BW the cuttof frequncy will increase and the loop will clean the oscillator phase noise

but this topology preffred to be used when the divission ratio of the divider is small
coz the divission ratio will increase the phase noise coming from the reffernce

and also u should be carfull will reffernce supriuos the loop must attenuate these spurs to get clean output

wish this help

 

[layes2]

and there is a trade off in bandwidth and D