[About]partial Reconfigurability in FPGA

[GunSeed]

Hi all

Anyone knows this problem to implement , using VHDL for Xilinx test board , thx.

 

[maestor]

Welcome to elektroda GunSeed :sm24:

I guess you had a look @

**broken link removed**

I haven't used partial reconfigurability although I have heard about it. And it seems that there is still a lot of work to be done in that area.

Why do you want to use it?

-maestor

 

[GunSeed]

Thanks, your answer .
Because, my research is about this topic.
So, I want to get more detailed information.

 

[xfpgas]

Yeah You can do Partial Reconfiguration in Xilinx FPGAS starting with Virtex. There are several ways you can do Partial reconfiguration. But first you may want to look at the following app notes from Xilinx.

Xilinx Partial Reconfiguration app note
https://www.xilinx.com/bvdocs/appnotes/xapp290.pdf

Before attempting partial reconfiguration, it is a good idea to understand the Virtex Configuration. Start with this app note
https://www.xilinx.com/bvdocs/appnotes/xapp151.pdf

And Xilinx has Java API called JBITS which allow you to create Xilinx Bitstream. This can come in handy if you are planning to do run time reconfiguration.

Kode

 

[maestor]

Hi xfpgas,

Have you actually used it in the past or heard about it?

-Maestor

 

[xfpgas]

Hi xfpgas,

Have you actually used it in the past or heard about it?

-Maestor

Yes I am currently using it for my Thesis. A lot of it is still being pursued in the Research world. I am not sure of any real real world products that are out there right now. But that will change over time, when the tools will mature enough. As of right now, it is not a very trivial job. It is not very hard either. I am using it in my MS Thesis to improve cost/performance ratio in Bioinformatics Industry. Most of the DNA sequencing/string matching in Bionformatics is done based on cluster based computing using powerful workstations. I am trying to exploit partial reconfiguration to come up with a better cost/performance using Reconfigurable Boards.

Any one else doing anythign similar or working with Partial Reconfiguration?

Hope this helps Maestor,
Kode

 

[maestor]

Thx for the info xfpgas.

Building times are increasing as FPGAs are getting bigger and bigger so it sounds like the way to go, just for inverting a bloody signal in a design because an LED doesn't go on could imply rebuilding a whole 2v8000 for example or start with a nasty manual routing...

We'll see what they come up with...

--maestor