i use tower 0.18um 4LM technology for my circuit design,has anyone used this technology ever before?
here, i have a question: for MIM capacitor (cmim_hc), its positive polarity uses TOP_M(the highest level metal) , M3, M2, and negetive polarity uses M3, M2, if i design a sc amplifier with single-ended output, the Cs and Cf must match well, for ex: Cs=8C0, Cf=C0, then, Av = 1 + Cs/Cf =9, in layout design, i use a cap array of 5x5, with unit capacitor C0, the inner 3x3 array for Cs and Cf, the outer 16 C0 for dummy cap, but now, by calibre PEX layout postsimulation, i find that, the parasitic cap of both positive and negetive polarity is very large, for C0=500fF, parasitic cap can have 150fF or so, then, Av = 1 + (Cs + Cparasitic) / Cf, the gain becomes larger than expected; i improved my layout for some day, but still not well.
i want to know, how to design or fix my layout to decrease the parasitic cap of Cs and Cf for both positive and negetice polarity, thanks.
can anyone help me?