# about MIM capacitor problem

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#### lhlbluesky

##### Banned
i use tower 0.18um 4LM technology for my circuit design,has anyone used this technology ever before?

here, i have a question: for MIM capacitor (cmim_hc), its positive polarity uses TOP_M(the highest level metal) , M3, M2, and negetive polarity uses M3, M2, if i design a sc amplifier with single-ended output, the Cs and Cf must match well, for ex: Cs=8C0, Cf=C0, then, Av = 1 + Cs/Cf =9, in layout design, i use a cap array of 5x5, with unit capacitor C0, the inner 3x3 array for Cs and Cf, the outer 16 C0 for dummy cap, but now, by calibre PEX layout postsimulation, i find that, the parasitic cap of both positive and negetive polarity is very large, for C0=500fF, parasitic cap can have 150fF or so, then, Av = 1 + (Cs + Cparasitic) / Cf, the gain becomes larger than expected; i improved my layout for some day, but still not well.

i want to know, how to design or fix my layout to decrease the parasitic cap of Cs and Cf for both positive and negetice polarity, thanks.

can anyone help me?

#### dick_freebird

##### Advanced Member level 5
I do not know what your CS and CF mean. But you want
to drive the bottom plate (where stray capacitance mostly
resides) and take charge-critical signal off the top (or
center) plate. You can still have significant fringing capacitance
off the top plate and only keep-away distance will fix
that if you have an even number of plates. Odd number,
you can make a "pocket" cap that has no non-through
(stray) capacitance.

If you can't eliminate, but care about, substrate capacitance
you could possibly drive a well region underneath it, with
an auxiliary amplifier in phase but not in the valued signal
path, so as to eliminate a voltage-difference and charge
loss; the capacitance is still there, but "killed" by the guard.
Similar to using triax cable for ultralow leakage measurements.

#### lhlbluesky

##### Banned
Cs is the sampling capacitor, and Cf is the feedback capacitor; besides, what does "pocket" cap mean? why it needed for odd number only? i also use a N-well underneath the cap array, but only improves a little; and what's the auxiliary amplifier's meaning? and how stray capacitor killed bythe guard? can you speak more clearly? thanks.

#### watersky

##### Member level 5
I think if Cs has parasitic cap, Cf should have parasitic cap too. The parasitic cap of every C0 is the same. So (8C0+8Cpara)/(C0+Cpara)=8.

#### lhlbluesky

##### Banned
for my case, it is a non-inverter sc amplifier, input signal in the non-inverter end, and Cs has one end grounded (in the inverter end, Av=1+Cs/Cf), so Av is very sensitive to Cs stray cap (to gnd), any other advice? and can you speak more clearly about my above questions?

#### timof

##### Advanced Member level 2
lhlbluesky said:
i use tower 0.18um 4LM technology for my circuit design,has anyone used this technology ever before?

here, i have a question: for MIM capacitor (cmim_hc), its positive polarity uses TOP_M(the highest level metal) , M3, M2, and negetive polarity uses M3, M2, if i design a sc amplifier with single-ended output, the Cs and Cf must match well, for ex: Cs=8C0, Cf=C0, then, Av = 1 + Cs/Cf =9, in layout design, i use a cap array of 5x5, with unit capacitor C0, the inner 3x3 array for Cs and Cf, the outer 16 C0 for dummy cap, but now, by calibre PEX layout postsimulation, i find that, the parasitic cap of both positive and negetive polarity is very large, for C0=500fF, parasitic cap can have 150fF or so, then, Av = 1 + (Cs + Cparasitic) / Cf, the gain becomes larger than expected; i improved my layout for some day, but still not well.

i want to know, how to design or fix my layout to decrease the parasitic cap of Cs and Cf for both positive and negetice polarity, thanks.

can anyone help me?

What you describe sounds more like MOM capacitor, rather than MIM capacitor (MOM capacitor uses standard metal layers like M1, M2, etc. in the form of interdigitated fingers, while MIM capacitor uses special MIM metal layer separated by (usually high K) very thin (~100-200A) dielectric from one of the standard metal layers, and is formed by two large parallel plates).

Normally, popular parasitic extraction tools are just not accurate enough to be used for precision analog designs. Try to rotate your layout by 90deg, and see if you extracted capacitance value changes. Or try to compare extraction results for several nets/capacitors with identical metal surroundings, and see if you get the same capacitance values.

One needs to use a field solver (a simulator that solves first-principle equations (Laplace equation for electrostatic potential)), rather than a pattern-matching based tools for reliable and accurate capacitance extraction.

You can find some additional info at these links:

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