about how to access DDR SDRAM

[vinod_g]

how to access row in ddr

I have to design an interface to DDR SDRAM controller such that to access a 1GB i required 30 bits , but when I checked IP CORE it has only 28 bit address for the 32 bit data from user side. moreover byte enables are 4.
my doubt is
1.how to convert the 30 bit address to 28 bit.
2.CAN we access by removing LSB bits and doing some logic with Byte Enables
Give ur ideas please

 

[Aastik]

Hi,

Well, I dont think you require 30 address bits to access 1GB DDR SDRAM. A word in DDR SDRAM is access by three addresses - Bank Address, Row Address and Column Address. Where Row and Column address share the same adress bus. So, i dont think you need to do anything with address bus to access 1GB SDRAM.

Thanks.

 

[anmolvlsi13]

DDR sDRAM access not depends on bits.
IT IS THE BANK(Row & Coloumn) through which you can access
the data.Again i am confused wat you are saying 30 & 28 bits...
wat is this data or address bits.
Any how It is the mode reg. that consists of data+address.....
if you don't want some bits you can fix it don't care value(x).

ANMOL

 

[msumanreddy]

I have to design an interface to DDR SDRAM controller such that to access a 1GB i required 30 bits , but when I checked IP CORE it has only 28 bit address for the 32 bit data from user side. moreover byte enables are 4.
my doubt is
1.how to convert the 30 bit address to 28 bit.
2.CAN we access by removing LSB bits and doing some logic with Byte Enables
Give ur ideas please

U r question is vague,can u explain in more detail

Added after 1 minutes:

U r question is vague can u put ur points in detail

 

[anmolvlsi13]

Look address is different to data bits.
it can be 32,64,128.........
any thing there are so many thing in ddr(mode register e.g)
Go to xilinx & refer application note for ddr ..........

Anmol

 

[satyakumar]

Hi,
1GB DDR SDRAM has 28 bits address, this address contains coloumn and row address fields. This address bus is used in initialization of DDR sdram at the start of accessing DDR sdram, the address is valid on both edges. The addressing method is dependent load mode register configuration. i.e the number of rows are coloumns to be accesed in particular read or write operations. More details are provided in Data sheets of any DDR sdram vendor.

see the edaboard topic for micron 256mb sdram data sheet
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