about FPGA flow questions

[stocking]

Who can answer the questions?
1. FPGA flow , from ISE to ModelSim , then Synplify Pro .
2. the interface between ISE and ModelSim , Synplify Pro .
3. Simutating FPGA must use ModelSim XE version?
thanks!

 

[Ace-X]

ISE have to be used only for PaR - all others steps, like entering desing, functional and post-PaR simulation, synthesis can be done with others tools. Usually, these tools have third-party interface one to each other. I would recommend to start with ActiveHDL. It is very friendly for beginners, has very nice simulator and has third-party interface for most tools.

 

[Renjith]

Hi stocking,
FPGA flow :
Design Entry --> Synthesis --> Translate --> Map --> P & R --> Fuse Device

In parallel u will be doing ur testing using simulation tools. (for behavioural design and final routed design)

Design entry: u can use HDL, IP cores, Schematics etc...
Synthesis and implementation : u can either use ISE or synplify etc

Once u have finished ur design entry, then u can simulate ur design using ModelSim. if ur behaviour is correct, then go for the synthesis and routing.
After routing u can again do the simulation for timing checks, Here u can use the Timing Analyzer tool from xilinx. if u have not met ur constraints, then go bck to ur design entry phase and do the modifications. finally once all ur constraints r met, then u can fuse ur FPGA

 

[stocking]

Firstly , thank you who answered my questions!

if I have used the primitive of FPGA device , I dont know how to add the library to the modelsim and Synplify pro!

 

[masai_mara]

For modelsim, if you are using xilinx then you will have to compile the unisims from the xilinx/vhdl/src folder into your work library, then say use library unims in your code ofcourse with the path to them updated in the midelsim.ini file.

hope this helps.