about different warning messages in xilinx

[kannan2590]

the code for fir filter is

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Code VHDL - [expand]
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library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_SIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
 ---- any Xilinx primitives in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;
 
entity subfilt1 is
 Port ( dout : out STD_LOGIC_vector(27 downto 0);
 clk : in STD_LOGIC;
 
reset : in STD_LOGIC;
 din : in STD_LOGIC_vector(7 downto 0));
 end subfilt1;
 
architecture Behavioral of subfilt1 is
 
component DFF is 
port(
 q : out STD_LOGIC_vector(7 downto 0); --output connected to the adder
 Clk :in std_logic; -- Clock input
 rst :in std_logic;
 d :in STD_LOGIC_vector(7 downto 0) -- Data input from the MCM block.
 );
 end component; 
 
signal H01,H049 : STD_LOGIC_vector(19 downto 0) := (others => '0');
 signal MCM02,MCM03 : STD_LOGIC_vector(27 downto 0) := (others => '0');
 signal add_out02 : STD_LOGIC_vector(27 downto 0) := (others => '0');
 signal Q02 : STD_LOGIC_vector(27 downto 0) := (others => '0');
 signal din1:std_logic_vector(7 downto 0):=(others =>'0');
 begin
 
H01 <= "11111111111111110101"; 
H049 <= "00000010100101011100"; 
--dff2 : DFF port map(Q02,Clk,MCM02);
 dff2 : DFF port map(q => din1,Clk=>clk,rst => reset,d => din);
 p01001:process(Clk,reset)
 begin
 if reset='0' then 
dout <="0000000000000000000000000000";
 
elsif clk'event and clk='1' then
 
MCM02 <= din*H01;
 MCM03 <= din1*H049;
 
add_out02 <= MCM02+ MCM03;
 dout <= add_out02;
 end if;
 end process p01001;
 
 
end Behavioral;

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when i synthesize this code i get warning messages like <dout 1>,<dout 2>,<dout 3>,<dout 4>,<dout 5>,<dout 25>,<dout 26>,are unconnected.so i am using vertex 4 fpga and the simulation results are coming correct inspite of these warning messages . whether these warning messages effect the output in fpga and if it effects how to correct and solve such warning messages?

 

[TrickyDicky]

its probably because those bits are stuck at 0 or 1.

 

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