about critical path and report_timing

design compiler report_timing

Hi

I have a design. I am using the Design compiler for synthesis. I know my design is a single clock design.
How can I see the slack value for the critical path in my design.

Do I need to create a path group consisting of all the d-inputs of the d-flops in my desogn for doing that while using report_timing command?

Thank
ASIC

report_timing -net -input_pins

report_timing should automatically divide the timing into path groups. What you are interested in is reg2reg.

report_timing on clock

to get the reg2reg timing,

1. set_false_paths -from [all_inputs]
set_false_paths -to [all_outputs]

2. use group_path and group all inputs and outputs (except input & output clocks) into one IO_PATHS group. now it shows reg2reg as one group and io paths as one group. easy to analyze

report_timing all paths

Hi silencer3 & iwpia57

Why do u want to create different path groups in this way? Even report_timing will itself report the timing of the paths for the clock path group in the design?

I once grouped all the paths reaching the d-inputs of all the flops in the design. Then I used report_timing. The report_timing command then resulted in two path groups. One path group is the path group (name of the path group: DINPUTS) created by all the D-inputs of the flops and the other was the path group (name of the path group: Clock_i) for the existing clock in the design.

Now the similar reg_to_reg critical paths should be reported both in DINPUTS and Clock_i path groups because the reg_to_reg paths are common for both of the above path groups. But in the report after report_timing I found the paths reported to differ totally from DINPUTS pathgroup and Clock_i path group. Can u explain this fallacy?

Regards.