About Constraints Hierarchy

Thanks for your focus
In ISE we can do Hierarchy Constraints.yes
but now I meet a problem, I wanna do constraints to a clcok net like this:

net sysclk tnm = sysclk ;
net sysclk period = 100 Mhz ;

if they are in the single VHDL program,it is very simple.And if the net is down in the next stage of the program,I mean it is in a instance using "port map",just using it like this:that is enough.

net d0tx/sysclk tnm = sysclk ;
net d0tx/sysclk period = 100 Mhz ;

but if my top project file is Schemetic,the Hierarchy is like this
top.sch(schemetic, top level)
|
J4control.vhd( using instance lvds:top_4_128_rx port map(...))
|
top_4_128_tx.vhd( the signal "sysclk" is in this VHDL file)
|
tx_4_128.vhd ( there are some RAM instances in this file)

1,what is relationship between the ucf file using on the top level and the ones using in the sub VHDL modules?
2,in this example,where should I make the constraint for the net "sysclk"?I mean in the top ucf file or in the sub VHDL modules?
3,In the ucf files,how can I use the constraint sentences acording to the hierarchy?

thanks again!

anybody help me?

I am not clear about this kind of constraints.
Any body can help me ~~

Hi friend
I need to help you but I don't know about your problem

sorry

just declare it at the top level as it will contrain the sys_clk but that if the sys_clk does not get routed into a DCM or a buffer, then you would have to constrain it at the output.