Mar 19, 2013 #1 M milan.dalwadi Newbie level 4 Joined Mar 18, 2013 Messages 5 Helped 0 Reputation 0 Reaction score 1 Trophy points 1,281 Activity points 1,311 Hello All, Pls Help me.. How to decide clock skew nd latancy during Clock Tree Synthesis..? How to meet setup timing in ic compiler from synopsis at CTS stage..??
Hello All, Pls Help me.. How to decide clock skew nd latancy during Clock Tree Synthesis..? How to meet setup timing in ic compiler from synopsis at CTS stage..??
Apr 4, 2013 #2 P Prashanthanilm Full Member level 5 Joined Aug 24, 2012 Messages 302 Helped 36 Reputation 72 Reaction score 36 Trophy points 1,308 Activity points 2,950 You will have .lib file in Standard cell to define you min and Max value in slew and capacitance. LIB->Liberty file contains information regarding Timing, Power Constraints
You will have .lib file in Standard cell to define you min and Max value in slew and capacitance. LIB->Liberty file contains information regarding Timing, Power Constraints