VLSI

[Trunke10]

Hi guys. Recently ive been taking the VLSI course. Recently, were talking about logic gate delays in class. Lecture material says that path effort for multistage logic network is GH=(g1*g2*g3...)*(Cout/Cin) I wonder why it can be done by this. It seems like RC delay time constants are getting multiplied together!

 

[MUXWA]

what the GH means？