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About Clock Tree Synthesis

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milan.dalwadi

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Hello All,

Pls Help me..

How to decide clock skew nd latancy during Clock Tree Synthesis..?

How to meet setup timing in ic compiler from synopsis at CTS stage..??
 
You will have .lib file in Standard cell to define you min and Max value in slew and capacitance.

LIB->Liberty file contains information regarding Timing, Power Constraints
 

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