Hi all,
Can anybody give me some suggestions about how to build a high-level model? For example,which tools should I use, C,systemC,systemverilog or whatever? I just want to build a model to verify a video processing system.
Use your most familiar language, I think. It will help you to build the model as soon as possible. Then you can pay more time in writing good HDL codes for the system.
You can use familiar language to design your product, like verilog HDL or VHDL. Although systemC is the newest language, but it is not familiar in industrial. If you have any question, many people can help you.
for video processing system, you better create a C model,
I think the C language is sufficient.
Then Verilog and Vhdl for hardware coding with your prefer.
You can compare the hardware simulation results and C model resutl.
For languages, I think C or SystemC (if you are willing to spend some extra time learning its syntax) are the best choices.
For tools, Celoxica's DK and Mentor's CatapultC claim to perform automatic hardware translation into VHDL and/or Verilog. However, you may have to optimize the generated code!