a VHDL question on code debug(many thanks)

[jackimoon]

a question on VHDL code(many thanks)

if I identify "mod" as this:
"port(mod:in std_logic_vector(3 downto 0) );"
then how can I use this sentence:
" if(s<mod)then
s<=s+1;co<='0';
elsif(s=mod)then
co<='1';s<="0000";
end if；"

(I'm a novice ,thanks for any help~~~~)

 

[barry]

I'm not sure what your question is. That looks like a perfectly valid snippet of code there.

Are you asking about the entity/architecture constructs?

 

[std_match]

"mod" is a reserved word in VHDL, so I am not surprised if you get into trouble when you use it as a port or signal name.

 

[jackimoon]

i changed the name and then succeed.*^_^*

"mod" is a reserved word in VHDL, so I am not surprised if you get into trouble when you use it as a port or signal name.