a urgent question about pipelined adc

[zxasqw123]

hi everyone
i can not understand why cap mismatch is not so important in S&H design?
if i want to design a 12bit or more resolution pipelined ADC,but my cap can not so match(0.1%),is this a big problem in my S&H design?
thanks a lot

 

[ezt]

Dear zxasqw123,

Of course the linearity of the front-end S/H stage is very important, since it directly affects the linearity of the input signal to the ADC. However, if the well-known Flip-Around structure is utilized as the S/H, the unity gain is almost independent of the capacitor mismatch, since the same capacitor is used for both sampling and hold operations. Hence, there is no capacitor ratio which deviates from unity due to mismatch.
On the other hand, if a charge-redistribution S/H structure is utilized which uses one capacitor for sampling and another for hold, the mismatch becomes important, since the input-output characteristic is as follows:
Vout = (Cs/Ch).Vin
So, large capacitors and/or mismatch compensation techniques should be applied.

Regards,
EZT

 

[safwatonline]

i think it is not important as the output gain will just be changed (i.e. the sampled signal will (Go+ΔG)*Vin
so if this gain doesn't cause any saturation i think its effect is like offset and can be tolerated by the digital correction.

 

[Btrend]

i can not understand why cap mismatch is not so important in S&H design?

cap mismatch is very important in the first stage of pipe-line ADC, cause any mismatch will be reflected to corresponding LSB.
mismatch including : unit cap and parasitic cap introduced by wire, fringe, coupling..
so post-sim is very important.
moreover,
if S&H has gain < 1 ==> the equivalent 1LSB voltage will be reduced for the following 1st stage pipe-line ==> this will increase the matching requirement of 1st stage.
if S&H has gain > 1 ==> 1LSB voltage will be increased ==> release the matching requirement of 1st stage , but it also increase quantization noise ==> the final SNR may degrade.

 

[jeffsky520]

hi, I can not agree with your viewpoint . I think Even if you use charge-redistribution S/H structure, cap mismatch only brings gain variation but not affect S/H performance obviously if all device can work well in saturation.

Dear zxasqw123,

Of course the linearity of the front-end S/H stage is very important, since it directly affects the linearity of the input signal to the ADC. However, if the well-known Flip-Around structure is utilized as the S/H, the unity gain is almost independent of the capacitor mismatch, since the same capacitor is used for both sampling and hold operations. Hence, there is no capacitor ratio which deviates from unity due to mismatch.
On the other hand, if a charge-redistribution S/H structure is utilized which uses one capacitor for sampling and another for hold, the mismatch becomes important, since the input-output characteristic is as follows:
Vout = (Cs/Ch).Vin
So, large capacitors and/or mismatch compensation techniques should be applied.

Regards,
EZT

Added after 3 minutes:

Hi, if S&H has gain > 1 ==> 1LSB voltage will be increased ==> release the matching requirement of 1st stage , and it also increase quantization noise,
But SNR will not become worse i guess, because meanwhile signal power increase with quantization noise increase, isn't it?

i can not understand why cap mismatch is not so important in S&H design?

cap mismatch is very important in the first stage of pipe-line ADC, cause any mismatch will be reflected to corresponding LSB.
mismatch including : unit cap and parasitic cap introduced by wire, fringe, coupling..
so post-sim is very important.
moreover,
if S&H has gain < 1 ==> the equivalent 1LSB voltage will be reduced for the following 1st stage pipe-line ==> this will increase the matching requirement of 1st stage.
if S&H has gain > 1 ==> 1LSB voltage will be increased ==> release the matching requirement of 1st stage , but it also increase quantization noise ==> the final SNR may degrade.

 

[zxasqw123]

hi jeffsky520
thanks for your reply ,i think this error is linear error ,and it will not cause nonlinearity.but for example if my cap has a 1%mismatch ,it means that i input a 1V voltage then my S&H can only get 0.99V,how can i get 12bit resolution?
can i change my input ,for example input 1.01V voltage?
thanks

 

[Usman Hai]

you can not get 12 bit when your capacitor dont match better than 0.025%.
you get 6 bit out of 1% matching. Let me know if you dont know how to get these numbers

 

[iamxo]

you can not get 12 bit when your capacitor dont match better than 0.025%.
you get 6 bit out of 1% matching. Let me know if you dont know how to get these numbers

So, could you explain in detail?? Thanks.

 

[Usman Hai]

In pipelined ADCs, the capacitors are used to set the gain of each
stage. For the residue voltage
\[V_{out} = V_{in}\left(\frac{C_s+C_f}{C_s}\right)\], \[C_s\] and \[C_f\] are set nominally
equal to get the gain of 2. Assume, \[C_s = C \pm \Delta C\] and \[C_f= C \mp \Delta C\]. Therefore, the residue voltage becomes

\[\begin{eqnarray}V_{out} &=& \left(\frac{C \pm \Delta C + C \mp \Delta C}{C \pm \Delta C}\right) V_{in} \\&=& \left(\frac{2C}{C \pm \Delta C}\right) V_{in}\\&=& 2\left(1 \mp \frac{\Delta C}{C}\right) V_{in} \end{eqnarray}
\]

For a full scale input, the \[V_{out}\] must not deviate from the
ideal value by more than a half LSB. However, for an N-bit ADC, the
capacitor matching must be accurate to N-1 bits. Therefore,


\[\begin{eqnarray} 2\left(1 + \frac{\Delta C}{C}\right) &<& 2 + 2^{-(N+1-1)} \\ \frac{\Delta C}{C} &<& 2^{-(N+1)}\end{eqnarray}\]
Hence, a 10-bit part must match to effectively 0.05\% accuracy.

Here I assume Vref=1V. So 12 bit part must match (1/2^12) *100%.

Sorry for some bad layout of equations, I used LateX first time in this forum

 

[iamxo]

You said "However, for an N-bit ADC, the capacitor matching must be accurate to N-1 bits. "

could you give the reason? I did not see in any material before. Thank you~

 

[Usman Hai]

I think you must have seen this before perhaps you might not have noticed it. Ok I will try to explain in detail.

Assuming a 10 bit pipelined ADC consists of 10 stages, where each stage resolves 1 effective bit. There are accuracy requirements for each stage. The way the accuracy requirements of each stage is derived by considering the later stages in the pipeline as ideal flash converter. For example, first stage generates the residue and transfer it to 9-bit ideal flash ADC. This first stage residue must be accurate for 9-bits so that ideal ADC can resolve the bits. The second stage residue must be 8-bit accurate, so on and so forth. Therefore, i-th stage must be accurate for N-i bits.

Accuracy means here is V-LSB_i = 1/2^(N-i).

Now one can divide the accuracy requirements among different error mechanism used to appear in pipelined adcs, that are op-amp gain error, settling error, capacitor matching error etc etc. So, usually during designing, this accuracy budget is divided among these different errors. Generally, each error requirements is half of the LSB. So the above formula can be written as for each accuracy requirement as 1/2^(N-i+1)

One can also design each stage with accuracy as 1/2^(N-i), which translates to a conservative design as op-amp gain is increased by 6dB, settling time is increased, and matching requirements are more stringent.

 

[iamxo]

I see.
So, actually, the capacitor matching in each stage should be (N-i) bits along the pipeline, if every stage has 1bit effective resolution, while not (N-1)bits in what you said before. That is to say, the capacitor matching could be relaxed in later pipeline stages, although we usually don't do, am I right?

 

[Usman Hai]

Yes, I used N-1 as a specialized case of first stage resolving 1 bit. Yes later stages have very relaxed matching, gain error and settling requirements. If you are concerned with low power design, then you must get benefit from this relaxations. Having said that, the beauty of pipelined stages is to design one stage (which is first stage) rigorously and copy the same design all over again. Thats why no one in practice extract the full benefit of these relaxations as the design time increases considerably.