Go to www.systemc.org, register and then you can download the latest release for any environment you like (Windows or Unix). This includes the
simulation engine and your development environment (VisualC++ or gcc) is all you need to simulate SystemC designs. If you want to view waveforms, a public domain VCD waveform viewer can be easily found (I can search if you want!). So, SystemC simulation is no problem! Did you mean synthesis? Because then, I am also interested!
As much as I know about Synopsys SystemC compiler, you must model your design at the RTL level if you want to generate Verilog netlist from SystemC code. If you model your design at higher levels than RTL you must manually refine your model. I am not sure whether there exists commercial tools that can performs tasks like High-level Synthesis (Behavioral Synthesis) using SystemC as input description.
There exists other commercial tools that support SystemC.
Right now all the top three EDA vendors have SystemC simulator.
. Syn@psys: vcs + SystemC co-simulation
. C@dence : NC native SytemC compiler (SystemC can be another native language supported by NC simulator)
. Ment@r : modelsim5.8 supported SystemC compiler
Right now all the top three EDA vendors have SystemC simulator.
. Syn@psys: vcs + SystemC co-simulation
. C@dence : NC native SytemC compiler (SystemC can be another native language supported by NC simulator)
. Ment@r : modelsim5.8 supported SystemC compiler