hav to design a 4-bit random number generator, to be
used for test pattern generation. The random number generator uses the Linear
Feedback Shift Register approach.the figure has been attached..
**Have to achieve high speed operation and nothing else.
**Area and power are not an issue in this design problem
wat is the max possible speed i can achieve (ie.,hav to minimize the clock speed to maximal extent)
i have to design this n have to do the layout part also in cadence
plzzzz help out