set_input_delay -max
set_input_delay specifies the input arrival time of a signal in relation
to the clock. It is used at the input ports, to specify the time it takes for the
data to be stable after the clock edge. The timing specification of the
design usually contains this information, as the setup/hold time
requirements for input signals.
set_clock_latency command is used to define the estimated clock
insertion delay during synthesis. This is primarily used during the prelayout
synthesis and timing analysis. The estimated delay number is an
approximation of the delay produced by the clock tree network insertion
(done during the layout phase).