A question regarding a SpartanII XC2S200 FPGA board

[Myself]

xc2s200 schematic

Hi everybody,

I have a SpartanII XC2S200 FPGA board produced by h**p://www.digilentinc.com/

with the following

Two 1A voltage regulators (3.3V and 2.5V)
50 MHz socketed oscillator
Parallel JTAG/EPP port
On-board 2-wire serial port
Six expansion connectors
LED/pushbutton on board
Ships with programming cable and power supply

My question is simply this:

I am trying to obtain a time-delay module by dividing the provided 50 MHz signal. I use parallel dividers to obtain some different signals. The following is the time delays I can obtain by dividing the 50 MHz signal.

25000000 Hz 0,00000004 s
12500000 Hz 0,00000008 s
6250000 Hz 0,00000016 s
3125000 Hz 0,00000032 s
1562500 Hz 0,00000064 s
781250 Hz 0,00000128 s
390625 Hz 0,00000256 s
195312,5 Hz 0,00000512 s
97656,25 Hz 0,00001024 s
48828,125 Hz 0,00002048 s
24414,0625 Hz 0,00004096 s
12207,03125 Hz 0,00008192 s
6103,515625 Hz 0,00016384 s
3051,757813 Hz 0,00032768 s
1525,878906 Hz 0,00065536 s
762,9394531 Hz 0,00131072 s
381,4697266 Hz 0,00262144 s
190,7348633 Hz 0,00524288 s
95,36743164 Hz 0,01048576 s
47,68371582 Hz 0,02097152 s
23,84185791 Hz 0,04194304 s
11,92092896 Hz 0,08388608 s
2,980232239 Hz 0,33554432 s
1,490116119 Hz 0,67108864 s
0,74505806 Hz 1,34217728 s
0,37252903 Hz 2,68435456 s
0,186264515 Hz 5,36870912 s
0,093132257 Hz 10,73741824 s
0,046566129 Hz 21,47483648 s
0,023283064 Hz 42,94967296 s
0,011641532 Hz 85,89934592 s
0,005820766 Hz 171,7986918 s
0,002910383 Hz 343,5973837 s
0,001455192 Hz 687,1947674 s


The problem I am facing is that when I try to obtain certain time delays, I further count the times shown above. For example to obtain 1,5 second time delay I count the signal 11,92092896 Hz(0,08388608s) 18 times. However I can not actullay get the time delays as I expected. There appears to be no problem in my design. I use schematic design.

I wonder if anyone has done a similar work and found a solution to this problem. Any desing idea is wellcome either schematic or in VHDL.

Thank you very much in advance for your help.

Myself

 

[k4iNz0w]

I would suggest to check your design. Have used that and many other Xilinx parts and faced similar problems -- trouble was always in the HDL.

I would also suggest to write code in an HDL instead of schematic entry.