I guess your double-feedback loop renders the circuit too stable. Try to use the nfets as diodes (i.e. connect their gates to their own drains).chang830 said:The negative impedence anlaysis is OK. But I can not make it oscillate.
Would anyone pls. tell me any wrong with the schematic? Is this topology suitible for the crystal osc design?
erikl said:I guess your double-feedback loop renders the circuit too stable. Try to use the nfets as diodes (i.e. connect their gates to their own drains).chang830 said:The negative impedence anlaysis is OK. But I can not make it oscillate.
Would anyone pls. tell me any wrong with the schematic? Is this topology suitible for the crystal osc design?
I think the pos. feedback via the cross-coupled pfets should be enough. Same as for a FF. Suggest to try it!chang830 said:My question is where is the negative impedance if we connect their gates to their own drains?
saro_k_82 said:I think you got the motivation from the popular LC oscillator. Fine but there L provides dc feedback to establish proper bias points. The inductance makes sure that the positive feedback loop gain for dc is low and so it is dc stable. Whereas in the schematic you have provided, the loop gain at dc is huge so some of the transistors will be in linear region --> no oscillation.
saro_k_82 said:No wait. Such a large resistor would be costly (if implemented on-chip) and would reduce the Q, add noise and the oscillator may not startup in all corners.
There is a much more elegant solution to the problem.
Just think of this structure.., Have a cross coupled negative gm generating nmos pair and instead of shorting the two sources, connect them with a capacitor. The two sources are biased with two matched current sources. The xtal is connected between the two drains and the drains are biased with two matched resistors to VDD (This can be replaced with current sources if required).
Now the capacitor makes the circuit dc stable and a proper capacitor value makes the circuit oscillate at the crystal frequency.
The two tail current sources can get their bias from the drains after some filtering., making the circuit self-sufficient and extremely low phase noise. The power consumption will be very low as well.
I read a paper on this some time back and have simulated the performance., I found this to be a very useful and interesting architecture.
I'll upload it if I find it now.
Adv:
1. Balanced sine wave output swings at the pad. No current in to the ESD diodes
2. Does not require loading caps by design, but one might include them to get better temperature and ageing characteristics.
3. Does not corrupt the supply/substrate and tolerant to supply/substrate noise.
4. Very low phase noise
5. Very low power
Disadv:
1. Requires an extra on-chip capacitor
2. Requires two pads
3. The structure is also a relaxation mode oscillator (without the xtal) and one needs to select the capacitor to avoid it (or there are other tricks here). There is no catastrophe if this mode exists as well., but it is better to avoid it.
Thanks,
Saro
saro_k_82 said:I did not find it difficult at all to keep it off from relaxation mode. There is a max limit on the capacitor set by the relaxation mode and min limit set by the necessity to have negative resistance at 35MHz. You can find them through simulation.
I have attached the architecture I used and the relevant papers.
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